The basic functions of a computer and memory devices include information processing and storage. In typical computer systems, these arithmetic, logic, and memory operations are performed by devices that are capable of reversibly switching between two states often referred to as “0” and “1.” Such switching devices are fabricated from semiconducting devices that perform these various functions and are capable of switching between two states at high speed.
Electronic addressing or logic devices, for instance for storage or processing of data, are made with inorganic solid state technology, and particularly crystalline silicon devices. The metal oxide semiconductor field effect transistor (MOSFET) is one the main workhorses.
Much of the progress in making computers and memory devices faster, smaller and cheaper involves integration, squeezing ever more transistors and other electronic structures onto a postage stamp sized piece of silicon. A postage stamp sized piece of silicon may contain tens of millions of transistors, each transistor as small as a few hundred nanometers. However, silicon based devices are approaching their fundamental physical size limits.
Inorganic solid state devices are generally encumbered with a complex architecture which leads to high cost and a loss of data storage density. The circuitry of volatile semiconductor memories based on inorganic semiconductor material must constantly be supplied with electric current with a resulting heating and high electric power consumption in order to maintain stored information. Nonvolatile semiconductor devices have a reduced data rate and relatively high power consumption and large degree of complexity.
Moreover, as inorganic solid state device sizes decrease and integration increases, sensitivity to alignment tolerances increases making fabrication markedly more difficult. Formation of features at small minimum sizes does not imply that the minimum size can be used for fabrication of working circuits. It is necessary to have alignment tolerances which are much smaller than the small minimum size, for example, one quarter the minimum size.
Scaling inorganic solid state devices raises issues with dopant diffusion lengths. As dimensions are reduced, the dopant diffusion lengths in silicon are posing difficulties in process design. In this connection, many accommodations are made to reduce dopant mobility and to reduce time at high temperatures. However, it is not clear that such accommodations can be continued indefinitely.
Applying a voltage across a semiconductor junction (in the reverse bias direction) creates a depletion region around the junction. The width of the depletion region depends on the doping levels of the semiconductor. If the depletion region spreads to contact another depletion region, punch through or uncontrolled current flow, may occur.
Higher doping levels tend to minimize the separations required to prevent punch through. However, if the voltage change per unit distance is large, further difficulties are created in that a large voltage change per unit distance implies that the magnitude of the electric field is large. An electron traversing such a sharp gradient may be accelerated to an energy level significantly higher than the minimum conduction band energy. Such an electron is known as a hot electron, and may be sufficiently energetic to pass through an insulator, leading to irreversibly degradation of a semiconductor device.
Scaling and integration makes isolation in a monolithic semiconductor substrate more challenging. In particular, lateral isolation of devices from each other is difficult in some situations. Another difficulty is leakage current scaling. Yet another difficulty is presented by the diffusion of carriers within the substrate; that is free carriers can diffuse over many tens of microns and neutralize a stored charge.
Continuing demand for smaller and lighter electronics has created a need for advanced materials and designs. This is because current trends in electron markets, such as the growing demand for wireless communications and portable computing, are placing an increasing emphasis on smaller/lighter device features and faster operating speeds. To ensure reliable operation of an electronic circuit, proper electrical isolation between adjacent conductors must be achieved. Proper electrical isolation mitigates high voltage arcing and leakage currents, which can be exacerbated at high frequencies. As device density on chips increases, the difficulty in achieving proper electrical isolation also increases.
As the wafer size increases and/or as transistor device size decreases, concerns over the interlayer dielectric material become more important. Current interlayer dielectric materials, such as inorganic oxides and nitrides, have beneficial aspects as well as deficiencies. It is more important to account for certain physical properties, such as unwanted diffusion, crosstalk, adequate insulation (both electrical and temperature), coefficients of thermal expansion, short channel effects, leakage, critical dimension control, drain induced barrier lowering, and the like, when making circuit designs. Mitigating deficiencies of interlayer dielectric materials is desired.